An over-12-Gbps on-chip transmission line interconnect with a pre-emphasis technique in 90 nm CMOS

This paper proposes an on-chip differential transmission line interconnect using a pre-emphasis technique for high-speed onchip signaling. The new transmitter with dynamic output-impedance control for pre-distortion of signals is presented. Simulation results showed that the proposed interconnect in 90 nm Si CMOS has possibilities of over-20-Gbps signaling and better energy-per-bit performances than conventional on-chip high-speed interconnects. Our 5-mm-long interconnect can achieve 12.5 Gbps signaling with power consumption of 6.9 mW in measurements.