DocumentCode :
3397077
Title :
Fast area-efficient VLSI adders
Author :
Han, Tackdon ; Carlson, David A.
Author_Institution :
Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, 01003, USA
fYear :
1987
fDate :
18-21 May 1987
Firstpage :
49
Lastpage :
56
Abstract :
In this paper, we study area-time tradeoffs in VLSI for prefix computation using graph representations of this problem. Since the problem is intimately related to binary addition, the results we obtain lead to the design of area-time efficient VLSI adders. This is a major goal of our work: to design very low latency addition circuitry that is also area efficient. To this end, we present a new graph representation for prefix computation that leads to the design of a fast, area-efficient binary adder. The new graph is a combination of previously known graph representations for prefix computation, and its area is close to known lower bounds on the VLSI area of parallel prefix graphs. Using it, we are able to design VLSI adders having area A = 0(n log n) whose delay time is the lowest possible value, i. e. the fastest possible area-efficient VLSI adder.
Keywords :
CMOS integrated circuits; CMOS technology; Delay; Integrated circuit interconnections; Lead; Water;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Arithmetic (ARITH), 1987 IEEE 8th Symposium on
Conference_Location :
Como, Italy
Print_ISBN :
0-8186-0774-2
Type :
conf
DOI :
10.1109/ARITH.1987.6158699
Filename :
6158699
Link To Document :
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