DocumentCode
3397219
Title
Arithmetic for vector processors
Author
Kirchner, R. ; Kulisch, U.
Author_Institution
Fachbereich Informatik, Universität Kaiserlautern, Fakultät für Mathematik, Universität Karlsruhe, West Germany
fYear
1987
fDate
18-21 May 1987
Firstpage
256
Lastpage
269
Abstract
In electronic computers the elementary-arithmetic operations are these days generally approximated by floating-point operations of highest accuracy. Vector processors and parallel computers often provide additional operations like “multiply and add”, “accumulate” or “multiply and accumulate”. Also these operations shall always deliver the correct answer whatever the data are. The user should not be oblighed to execute an error analysis for operations predefined by the manufacturer. In the first part of this paper we discuss circuits which allow a fast and correct computation of sums and scalar products making use of a matrix shaped arrangement of adders and pipeline technology. In the second part a variant is discussed which permits a drastic reduction in the number of adders required. The methods discussed in this paper can also be used to build a fast arithmetic unit for micro computers in VLSI-technology.
Keywords
Adders; Error analysis; Registers; Supercomputers; Switches; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Arithmetic (ARITH), 1987 IEEE 8th Symposium on
Conference_Location
Como, Italy
Print_ISBN
0-8186-0774-2
Type
conf
DOI
10.1109/ARITH.1987.6158704
Filename
6158704
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