DocumentCode
3397357
Title
On the implementation of shifters, multipliers, and dividers in VLSI floating point units
Author
Peng, Victor ; Samudrala, Sridhar ; Gavrielov, Moshe
Author_Institution
Digital Equipment Corporation, 75 Reed Road, Hudson, MA01749, USA
fYear
1987
fDate
18-21 May 1987
Firstpage
95
Lastpage
102
Abstract
Several options for the implementation of combinatorial shifters, multipliers, and dividers for a VLSI floating point unit are presented and compared. The comparisons are made in the context of a single chip implementation in light of the constraints imposed by currently available MOS technology.
Keywords
Arrays; Logic gates; Periodic structures; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Arithmetic (ARITH), 1987 IEEE 8th Symposium on
Conference_Location
Como, Italy
Print_ISBN
0-8186-0774-2
Type
conf
DOI
10.1109/ARITH.1987.6158711
Filename
6158711
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