An overview of theory and techniques for reducing ring oscillator supply voltage sensitivity in mixed-signal SoC

Ring oscillators, as extensively used building blocks in today´s mixed-signal system on chip (SoC), have to face with the situation that its jitter and phase noise performance are seriously deteriorated by on-chip digital switching supply noise. Theory of supply noise induced jitter has been presented. A comparative study of different kinds of architecture and multi-dimensional design considerations is provided. With optimization design and proper noise compensation, the supply noise-induced sensitivity and the rms jitter of ring oscillator-based phase-locked loop can be lower than 0.1%-carrier frequency/1% Vdd and 5ps respectively. These approaches can be summarized as: isolation, regulation, compensation, calibration and self enhanced. Advantages and drawbacks of these techniques are analyzed which can provide more choice and illumination for different kinds of applications.