BiCMOS SRAM with array-integrated sense devices

Author

Ouellette, Michael R. ; Wissel, Larry

Author_Institution

IBM, Essex Junction, VT, USA

fYear

1991

fDate

14-17 May 1991

Firstpage

1008

Abstract

A 128-word by 44-b wide SRAM (static random-access memory) embedded array has been designed in a BiCMOS process that contains 0.45-μm FETs and 18-GHz bipolar transistors. The design integrates the sense-amp function into the array, and BiCMOS performance levels are maintained without utilizing the DC power of traditional BiCMOS sense-amplifier and level-shift circuits. The sense-amp function is realized through a unique combination of bipolar devices and FET storage cells distributed along a bit line. Each bipolar device acts as an address/data-controlled current switch that may or may not discharge a bit line. The discharge occurs very quickly, generating a full signal level capable of driving CMOS logic

Keywords

BiCMOS integrated circuits; SRAM chips; VLSI; 0.45 micron; 18 GHz; 5632 bits; BiCMOS process; FETs; SRAM; array-integrated sense devices; bipolar current switch; bipolar transistors; bit line; driving CMOS logic; embedded array; performance levels; sense-amp function; sense-amplifier; BiCMOS integrated circuits; Bipolar transistors; Capacitance; Driver circuits; FETs; Logic devices; Power amplifiers; Random access memory; Signal generators; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-0620-1

Type

conf

DOI

10.1109/MWSCAS.1991.251965

Filename

251965