A phasing adjustment and fanout buffer for distributing clock and control signals in high-speed digital systems

The design, implementation, and testing of a gallium arsenide phasing and fanout buffer are described. The integrated circuit provides a method for adjusting the phasing of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described buffer can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fanout buffer and provides 12 in-phase outputs. The buffer is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components