Estimating SEE Error Rates for Complex SoCs With ASERT

This paper describes the ASIC Single Event Effects (SEE) Error Rate Tool (ASERT) methodology to estimate the error rates of complex System-on-Chip (SoC) devices. ASERT consists of a top-down analysis to divide the SoC into sensitive cell groups. The SEE error rate is estimated with a bottom-up calculation summing the contribution of all sensitive cell groups, including derating and utilization factors to account for the probability that a cell-level error has a SoC-level impact. The sensitive cell SEE rates are evaluated using test data from specially designed test structures. Standard rate estimation tools are augmented with novel rate estimation approaches for direct proton upsets and for spatial redundancy.