A direct digital frequency synthesizer based on optimized two segment sixth-order polynomial approximation

A novel ROM-less direct digital frequency synthesizer (DDFS) is presented using phase to sinusoid amplitude conversion blocks based on optimized sixth-order polynomial approximation. A slide factor ξ≈0.703 is introduced to separate 0-90 phase degree into two parts, which are further approximated with a sixth-order even polynomial. The mathematic analysis shows that the maximum residual 1.05e-6 can be achieved, thus an output resolution up to 20 bits can be gotten. Furthermore, the computational units of the polynomial approximation have been decomposed into twenty-six stages to support a 330MHz clock rate. The spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is up to 138 dBc.