VLSI implementation of neural-type cell with MOS linear resistor

A CMOS integrated circuit for the weighted synapse and the summation of the synaptic signals is presented. Neural-type cells (NTCs) are used as the processing elements along with a voltage-controlled linear MOS resistor. This variable resistor is used to control the synaptic weights as pulse densities, and thus the weights are controlled by the gate control voltage. By adding buffered inverter stages, the output signal of the NTC is converted into the normalized pulse stream of the 5 V_p-p signal for easy handling. The summation is executed by a capacitor integration circuit where the currents from different NTCs are accumulated. Simulation results are presented