A compact implementation of masked AES S-box

Author

Wei Wei ; Xiaoxin Cui ; Di Wu ; Rui Li ; Kaisheng Ma ; Dunshan Yu ; Xiaole Cui

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A masking scheme of AES algorithm is analyzed, and the optimal masked S-box is implemented in this paper. By using the “tower field” representation, all nonlinear process of unmasked S-box is mapped to multiplication in GF(2), which is a single AND gate in circuits, and power consumption is hidden by using additive masked. In order to further reduce the hardware cost, a simplified masked AND gate is adopted and masks are reused safely. Both gate-level simulation and FPGA testing result have proved that our implementation provides good resistance against DPA attack.

Keywords

cryptography; field programmable gate arrays; logic circuits; logic gates; logic testing; power consumption; AES algorithm; AND gate; DPA attack; FPGA testing; circuits; gate-level simulation; masked AES S-box; masking scheme; nonlinear process; power consumption; unmasked S-box; Additives; Algorithm design and analysis; Field programmable gate arrays; Galois fields; Hardware; Logic gates; Resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6466685

Filename

6466685