A high-resolution, high-linearity, two-step Time-to-Digital Converter for wideband counter-assisted ADPLL in 0.13um CMOS

Author

Wei-wei Ji ; Peng-fei Liu ; Yang-Yang Niu ; Wei Li ; Ning Li ; Jun-yan Ren

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

This paper presents a high-resolution, high-lineartity, two-step Time-to-Digital Converter(TDC) for wideband counter-assisted ADPLL. The proposed design uses two-step conversion scheme with buffer delay chain and Vernier delay chain, which realizes high resolution, wide range and period normalization in wideband ADPLL. The multiplexer between the two quantization stages is simple and inherently linear. This TDC is designed in 0.13um CMOS technology. Simulation results shows that 8ps resolution is achieved for 1.2G-2.5GHz ADPLL with reference frequency 40MHz.

Keywords

CMOS digital integrated circuits; UHF integrated circuits; buffer storage; delays; digital phase locked loops; multiplexing equipment; time-digital conversion; CMOS technology; TDC; Vernier delay chain; buffer delay chain; frequency 1.2 GHz to 2.5 GHz; frequency 40 MHz; high-resolution high-linearity two-step time-to-digital converter; multiplexer; quantization stages; size 0.13 mum; time 8 ps; two-step conversion scheme; wideband counter-assisted ADPLL; Delay; Linearity; Multiplexing; Quantization; Signal resolution; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6466690

Filename

6466690