Title :
A power and area efficient CMOS charge-pump phase-locked loop
Author :
Siliang Hua ; Hua Yang ; Yan Liu ; Quanquan Li ; Donghui Wang
Author_Institution :
Inst. of Acoust., Beijing, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
In this paper, a power and area efficient charge-pump phase-locked loop (CPPLL) is proposed. The design utilizes a top-down methodology to determine system parameters. The PLL is implemented in 0.18μm CMOS technology and its supply voltage is 1.8V. The PLL has in input clock frequency of 25MHz and an output clock frequency of 0.8-1.6GHz with 50μm*110μmactive area. Measurement results show that the PLL without output buffers consumes 11.7mW and the root-mean-square jitter of the VCO at 1.6GHz is 7.37ps.
Keywords :
CMOS analogue integrated circuits; buffer circuits; charge pump circuits; jitter; mean square error methods; phase locked loops; voltage-controlled oscillators; CPPLL; VCO; area efficient CMOS charge-pump phase-locked loop; frequency 0.8 GHz to 1.6 GHz; input clock frequency; power 11.7 mW; power efficient CMOS charge-pump phase-locked loop; root-mean-square jitter; size 0.18 mum; time 7.37 ps; top-down methodology; voltage 1.8 V; CMOS integrated circuits; Charge pumps; Clocks; Jitter; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6466694
