DocumentCode
3398525
Title
Study of the disturb in SONOS memory
Author
Li-Juan Liu ; Guo-Fei Shen ; Gang Cao ; Liao, Shengcai
Author_Institution
Dept. of Reliability Eng., Shanghai Hua Hong NEC Electron. Co. Ltd., Shanghai, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
Disturb is a serious problem in SONOS. In this paper, read disturb, program disturb, and the effect of the operation between the adjacent cells are investigated. Gate voltage, drain voltage and E/P cycling will accelerate the threshold voltage (Vtp) drift of SONOS. 1.6V drain voltage in program mode and 1.6V gate voltage in read mode show free or minimal effect from all disturbs. The short erase and program time will reduce disturbs.
Keywords
digital storage; E/P cycling; SONOS memory; drain voltage; gate voltage; program disturb; program time; read disturb; short erase; threshold voltage; voltage 1.6 V; Arrays; Leakage current; Logic gates; Nonvolatile memory; Programming; SONOS devices; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6466695
Filename
6466695
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