DocumentCode :
3398665
Title :
Transaction-based waveform analysis for IP selection
Author :
Liu, Jian ; Shragowitz, Eugene
Author_Institution :
Dept. of Comput. Sci. & Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
2003
fDate :
21-24 Jan. 2003
Firstpage :
104
Lastpage :
107
Abstract :
In a process of IP selection, it is necessary to establish whether a candidate IP is equivalent to a behavioral model of a design proposed by a customer. It is desirable to perform this verification to exclude IPs, which "don\´t match" the rest of the design. This work combines a simulation approach to establishing equivalence between models with formal regular expression techniques to provide transaction-level preliminary evaluation of IP suitability. Such evaluation could precede a decision to acquire IP.
Keywords :
circuit CAD; circuit simulation; industrial property; integrated circuit design; integrated circuit modelling; waveform analysis; IP reuse; IP selection; IP suitability evaluation; SoC design; design behavioral model; design verification; model equivalence; simulation; transaction-based waveform analysis; transaction-level preliminary evaluation; Circuit simulation; Clocks; Computer science; Context modeling; Design engineering; Formal verification; Hardware; Prototypes; Sequential circuits; Signal analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
Type :
conf
DOI :
10.1109/ASPDAC.2003.1195001
Filename :
1195001
Link To Document :
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