A 90-μW 16 bit 20 KHz-BW feedforward double-sampled sigma-delta modulator in 0.18 CMOS

Author

Long Xu ; Fei Liu ; Hai-Gang Yang

Author_Institution

Inst. of Electron., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

This paper presents a low power, area-efficient feedforward double-sampling sigma delta modulator. A novel double sampled structure that combines two techniques was proposed. The DAC capacitor reset technique is used to eliminate the noise folding caused by the mis match between two sampling branches; a direct summation scheme obviates analog adder in the front of the quantizer, which greatly relaxes the timing constraints in the feedforward path. The modulator is implemented in the SMIC 0.18um technology; the simulation results show the modulator provides 102.5dB SNDR over a 20-KHz signal bandwidth. The power consumption of modulator is 90μW under 1.5V power supply.

Keywords

CMOS integrated circuits; adders; delta-sigma modulation; feedforward; low-power electronics; CMOS technology; DAC capacitor reset technique; SMIC technology; analog adder; bandwidth 20 kHz; direct summation scheme; double sampled structure; feedforward path; low power area-efficient feedforward double-sampling sigma delta modulator; noise folding; power 90 muW; quantizer; sampling branches; size 0.18 mum; timing constraints; voltage 1.5 V; word length 16 bit; Capacitors; Clocks; Feedforward neural networks; Modulation; Noise; Sigma delta modulation; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6466706

Filename

6466706