DocumentCode
3398901
Title
An Low-Power 128Kb SRAM with 0.2um FDSOI and its TID radiation response
Author
Zhao Kai ; Li Ning ; Qiao Ning ; Gao Jiantou ; Yang Bo ; Yu Fang ; Liu Zhongli
Author_Institution
Inst. of Microelectron., Beijing, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
2
Abstract
A 128K-bit Low-Power SRAM with 0.2um Fully-Depleted(FD) SOI CMOS process is presented. First-cut datalO and Busr-Splitting techniques are used in the SRAM circuit design to achieve 15uA standby mode current and 20uA~500uA active mode current after packaged in DIP28. The SRAM´s Total-lonizing-Dose capability is about 20K rad(Si).
Keywords
low-power electronics; semiconductor storage; E/P cycling; SONOS memory; drain voltage; gate voltage; program disturb; program time; read disturb; short erase; threshold voltage; CMOS integrated circuits; CMOS process; Circuit synthesis; Microelectronics; Radiology; Random access memory; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6466715
Filename
6466715
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