Title :
Logic optimization for asynchronous speed independent controllers using transduction method
Author :
Saito, Hiroshi ; Nakamura, Hiroshi ; Fujita, Masahiro ; Nanya, Takashi
Author_Institution :
RCAST, Univ. of Tokyo, Japan
Abstract :
Asynchronous speed independent (SI) circuits based on an unbounded gate delay model often suffer from high area penalty. It happens due to the lack of efficient global optimization. This paper presents a Boolean optimization method based on the transduction method to optimize asynchronous SI circuits while preserving hazard-freeness.
Keywords :
Boolean functions; asynchronous circuits; circuit optimisation; delay estimation; graph theory; logic CAD; Boolean optimization method; STG; asynchronous speed-independent circuits; global optimization; logic optimization; signal transition graph; state graph; transduction method; unbounded gate delay model; Asynchronous circuits; Circuit synthesis; Delay; Logic circuits; Logic functions; Optimization methods; Petri nets; Signal synthesis; State-space methods; Timing;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195016
