DocumentCode
3398922
Title
Logic optimization for asynchronous speed independent controllers using transduction method
Author
Saito, Hiroshi ; Nakamura, Hiroshi ; Fujita, Masahiro ; Nanya, Takashi
Author_Institution
RCAST, Univ. of Tokyo, Japan
fYear
2003
fDate
21-24 Jan. 2003
Firstpage
197
Lastpage
202
Abstract
Asynchronous speed independent (SI) circuits based on an unbounded gate delay model often suffer from high area penalty. It happens due to the lack of efficient global optimization. This paper presents a Boolean optimization method based on the transduction method to optimize asynchronous SI circuits while preserving hazard-freeness.
Keywords
Boolean functions; asynchronous circuits; circuit optimisation; delay estimation; graph theory; logic CAD; Boolean optimization method; STG; asynchronous speed-independent circuits; global optimization; logic optimization; signal transition graph; state graph; transduction method; unbounded gate delay model; Asynchronous circuits; Circuit synthesis; Delay; Logic circuits; Logic functions; Optimization methods; Petri nets; Signal synthesis; State-space methods; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN
0-7803-7659-5
Type
conf
DOI
10.1109/ASPDAC.2003.1195016
Filename
1195016
Link To Document