High performance 0.2 /spl mu/m CMOS with 25 /spl Aring/ gate oxide grown on nitrogen implanted Si substrates

The difficulties in device engineering increase rapidly as advanced circuits take up more portions in the design of low-power IC products. These new circuit designs enforce strict requirements on the deep-submicron FETs, particularly in the areas of: (1) properties of thin gate oxides, (2) control of short channel effects, (3) doping profiles to reduce subthreshold slope and back-gate bias coefficient, and (4) device aging. Previously, we have shown that thin gate oxides grown on nitrogen implanted (N/sup +/ I/I) Si substrates can prevent boron (B) penetration for p-MOSFETs. Here, we have (1) built high performance 0.2 /spl mu/m CMOS with 25 /spl Aring/ gate oxide, (2) used multi-angle ellipsometry, high-resolution TEM, SIMS, XPS, and tunneling current to study the oxide properties, (3) identified N distribution in the oxide, (4) observed quantum effects in the oxide tunneling current, (5) compared hole and electron mobilities with and without N/sup +/ I/I, (6) demonstrated a range of V/sub th/, I/sub on/, and I/sub off/, (7) achieved 72 mV/dec subthreshold slope (SS), 60 mV Vth-shift under 2.5 V back-gate bias, and below 10 mV DIBL V/sub G/-shift, (8) studied junction leakage with and without N/sup +/ I/I, (9) oxide breakdown voltage, and (10) device lifetimes for both n- and p-MOSFETs.