DocumentCode :
3399054
Title :
Adaptive wire adjustment for bounded skew clock distribution network
Author :
Saaied, H. ; Al-Khalili, D. ; Al-Khalili, A. ; Nekili, M.
Author_Institution :
Concordia Univ., Montreal, Que., Canada
fYear :
2003
fDate :
21-24 Jan. 2003
Firstpage :
243
Lastpage :
248
Abstract :
In this paper, we suggest an adaptive approach for the clock distribution network (CDN) to cope with a modification in the VLSI system design. The CDN´s wires are adjusted iteratively to reduce the skew that is resulting from a minor modification in the clock pins of a complex VLSI system. Such skew can be remedied by selecting a balancing node (BN) and adjust its edges so that the skew gets smaller. The required edge adjustments are determined using the Elmore delay model. The performance of the algorithm is investigated using different random sets of clock pins. Also, the algorithm is tested by altering some clock pins in a zero skew CDN. For small modifications in a large number of nodes in the CDN, our algorithm can achieve zero skew with less iterations than linear order algorithms.
Keywords :
VLSI; circuit CAD; clocks; delays; integrated circuit design; integrated circuit modelling; iterative methods; system-on-chip; Elmore delay model; SoC; VLSI system design modification; adaptive wire adjustment; balancing node edge adjustment; bounded skew clock distribution network; clock pins; clock skew; iterations; iteratively adjusted CDN wires; linear order algorithms; system on chip complexity; zero skew CDN; Capacitance; Clocks; Delay; Educational institutions; Pins; Process design; System-on-a-chip; Testing; Very large scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
Type :
conf
DOI :
10.1109/ASPDAC.2003.1195023
Filename :
1195023
Link To Document :
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