Title :
Trench storage node technology for gigabit DRAM generations
Author :
Muller, K.P. ; Flietner, B. ; Hwang, C.L. ; Kleinhenz, R.L. ; Nakao, T. ; Ranade, R. ; Tsunashima, Y. ; Mii, T.
Author_Institution :
Adv. Semicond. Technol. Center, IBM Corp., Hopewell Junction, NY, USA
Abstract :
The two mainstream technologies for DRAMs today are based on stacked capacitors and trench capacitors. While topography limitations require development of high /spl epsiv/ dielectric materials and complex capacitor structures for the stacked capacitor approach, ultra high aspect ratio deep trench structures allow the extension of conventional process technologies. Key points for trench storage node technology are reactive ion etching (RIE) of trench structures with a high rate and very tight taper angle control limits as well as the formation of reliable ultra thin nitride-oxide (NO) dielectric films. In this work we show to what degree these factors can be controlled and optimized focusing on a new dipole ring magnetron (DRM) reactor for deep trench etching and a new fast thermal processor (FTP) for node dielectric formation.
Keywords :
CMOS memory circuits; DRAM chips; chemical vapour deposition; dielectric thin films; integrated circuit reliability; nitridation; oxidation; rapid thermal processing; sputter etching; SiON; deep trench etching; dipole ring magnetron reactor; fast thermal processor; gigabit DRAM generations; node dielectric formation; reactive ion etching; reliable ultra thin nitride-oxide dielectric films; reoxidized LPCVD nitride film; trench storage node technology; ultra high aspect ratio deep trench structures; very tight taper angle control limits; Capacitors; Dielectric films; Dielectric materials; Etching; Magnetic materials; Random access memory; Shape control; Surface topography; Temperature control; Transistors;
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3393-4
DOI :
10.1109/IEDM.1996.553853