Title :
Super junction LDMOS technologies for power integrated circuits
Author :
Ming Qiao ; Wen-Lian Wang ; Zhao-Ji Li ; Bo Zhang
Author_Institution :
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
Super junction (SJ) concept is attractive for power devices because of its advantage for improving the tradeoff between the breakdown voltage (BV) and the on resistance (Ron). It is an acknowledged wish to apply the SJ concept to LDMOS for the power integrated circuits (PICs). However, the conventional SJ LDMOS is no practical due to the influence of the fabrication process, charge imbalance, and junction termination, etc. This paper introduces the key technologies for the SJ LDMOS based on our researched SJ device named SLOP (Surface Low On-resistance Path) LDMOS, aiming to offer applicable lateral SJ device for the PICs.
Keywords :
MOSFET; electric breakdown; power integrated circuits; SLOP LDMOS; breakdown voltage; charge imbalance; junction termination; on resistance; power devices; power integrated circuits; super junction LDMOS technology; surface low on-resistance path; Doping; Electric fields; Fabrication; Junctions; Layout; Performance evaluation; Substrates;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6466727
