VLSI support for voice over internet protocol scheduling and buffering in high speed packet switched network

This paper presents a number of new approaches for designing fast, scalable queuing structures in VLSI for very high speed packet-switched networks. Such queuing structures are necessary for implementing packet buffers in switches and routers that have multi Gigabit-per-second (Gbps) ports. The paper addresses the design of two specific queue architectures: balanced parallel multi-input multi-output (MIMO) buffers and systolic parallel priority queues (PPQ). A methodology for the systematic design of order-preserving parallel MIMO buffers is presented. The MIMO buffer employs an arithmetic-free systolic routing network and bank of parallel FIFO buffers to yield a load-balanced realization with increased bandwidth. Using this methodology we derived scalable parallel buffer structures that can be designed to match the rate of ultra high- speed links using current memory technology that uses moderate clock rates. A small prototype of the MIMO buffer attains a rate of 10.6 Gbps which is more than adequate to support a Sonet OC-192 link. The combined use of pipe lined architecture and dynamic CMOS circuits resulted in significant reduction in design complexity and substantial performance gains in speed and area.