Title :
A redundant variable scaling CORDIC rotation engine implementation
Author :
Harding, John A. ; Lang, Tomas
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Abstract :
The CMOS implementation of a high-performance rotation processor using redundant CORDIC is described in detail. This design replaces carry-propagate addition with carry-save addition, which is a fast form of parallel addition. Characteristics of 1.2-μm CMOS implementations are given
Keywords :
CMOS integrated circuits; digital arithmetic; digital signal processing chips; parallel architectures; redundancy; signal processing; CMOS implementation; CORDIC rotation engine; carry-save addition; high-performance rotation processor; parallel addition; redundant variable scaling; Algorithm design and analysis; CMOS process; Computer architecture; Computer science; Digital arithmetic; Engines; Equations; Matrix decomposition; Parallel architectures; Throughput;
Conference_Titel :
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-0620-1
DOI :
10.1109/MWSCAS.1991.252043
