Investigations on the correlation between line-edge-roughness (LER) and line-width-roughness (LWR) in nanoscale CMOS technology

In this paper, the correlation between line-edge-roughness (LER) and line-width-roughness (LWR) is studied for the first time. Based on the characterization methodology of auto-correlation functions (ACF), a new theoretical model of LWR is proposed, in which the ACF of LWR can be analytically obtained from the ACFs of LER in the two line-edges. An improved method of generating “practical” lines with correlated LER is also proposed for statistical simulations. The model indicates that the LWR ACF is composed of two parts: one involves LER information, the other involves the cross-correlation of LER in the two line-edges, which agrees well with simulation results. It is also found that the correlation length of LWR reduces with increasing the correlation coefficient of the two LER sequences with different correlation lengths. The results provide helpful guidelines for the characterization, modeling and the optimization of LER/LWR in nanoscale CMOS technology.