Title : 
Multi-level placement for large-scale mixed-size IC designs
         
        
            Author : 
Chang, Chin-Chih ; Cong, Jason ; Yuan, Xin
         
        
            Author_Institution : 
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
         
        
        
        
        
        
            Abstract : 
In this paper we study the large-scale mixed-size placement problem where there is a significant size variation between big and small placeable objects (the ratio can be as large as 10,000). We have developed a multi-level optimization algorithm, MPG-MS, for this problem which can efficiently handle both large-scale designs and large size variations. Compared with the recently published work on large-scale mixed macro and standard cell placement benchmarks for wirelength minimization, our method can achieve 13% wirelength reduction on average with comparable runtime.
         
        
            Keywords : 
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; MPG-MS algorithm; VLSI physical design; large-scale mixed-size IC designs; multi-level optimization algorithm; multi-level placement; placement problem; wirelength minimization; Algorithm design and analysis; Circuits; Computer science; Delay; Design optimization; Large-scale systems; Minimization methods; Runtime; Standards publication; Very large scale integration;
         
        
        
        
            Conference_Titel : 
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
         
        
            Print_ISBN : 
0-7803-7659-5
         
        
        
            DOI : 
10.1109/ASPDAC.2003.1195036