Title :
Optimizing computation and communication in shuffle-exchange processors
Author :
Fettweis, Gerhard ; Bitterlich, Stefan
Author_Institution :
IBM Almaden Res. Center, San Jose, CA, USA
Abstract :
The implementation of shuffle exchange processors (e.g. fast Fourier transform, sorting, Viterbi algorithm) is dominated by two problems, a massive computational task and a severe routing/communication problem. A novel combined solution is presented for both problems. The novel bit-slice architecture offers a good improvement in processor speed and efficiency, as well as a reduction of the communication complexity by at least an order of magnitude. A VLSI design example shows the significance of the results by providing a shuffle exchange processor for the Viterbi algorithm in 1.2 μm CMOS
Keywords :
CMOS integrated circuits; VLSI; hypercube networks; 1.2 micron; CMOS; VLSI design; Viterbi algorithm; bit-slice architecture; fast Fourier transform; multiprocessor interconnection network; shuffle-exchange processors; sorting; Algorithm design and analysis; Circuit analysis; Computer architecture; Delay; Distributed computing; Integrated circuit interconnections; Sorting; Throughput; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-0620-1
DOI :
10.1109/MWSCAS.1991.252047
