Performance of a silicon CMOS/VCSEL smart pixel for a recirculating sorter

Previously we have reported a proposed bitonic recirculating optoelectronic sorter. In this paper we present the performance of the smart pixels used to demonstrate the recirculating sorter. The smart pixels were implemented with CMOS circuitry fabricated through the MOSIS foundry, with integrated N well Si photodiodes, and wire bonded vertical cavity surface emitting lasers (VCSELs). This testbed was used to verify the functionality of the design and to determine the performance obtainable with this technology. Similar to our previously proposed reticulating bitonic sorter, the recirculating sorter we present here is comprised of two processing stages. Each stage is comprised of separately mounted chips of CMOS smart pixel and VCSEL arrays.