DocumentCode
3399465
Title
Leading edge low power design [SoCs]
Author
Benini, Luca
Author_Institution
Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
fYear
2003
fDate
21-24 Jan. 2003
Firstpage
385
Lastpage
389
Abstract
Well into the System-on-Chip era, power consumption has emerged as one of the most critical challenges to design complexity scaling. Moving from a critical assessment of current technologies and architectures, we survey the distinguishing features of a design methodology that aims at energy consumption reduction, under guaranteed quality of service (QoS), as a main objective in system design.
Keywords
CMOS integrated circuits; integrated circuit design; low-power electronics; system-on-chip; SoC design; design complexity scaling; design methodology; energy consumption reduction; guaranteed QoS; low power design; power consumption; quality of service; system-on-chip; CMOS technology; Computer architecture; Design methodology; Energy consumption; Hardware; Quality of service; Silicon; System-on-a-chip; Transistors; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN
0-7803-7659-5
Type
conf
DOI
10.1109/ASPDAC.2003.1195045
Filename
1195045
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