Minimizing total power by simultaneous Vdd/Vth assignment

Author

Srivastava, Ashish ; Sylvester, Dennis

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

400

Lastpage

403

Abstract

We investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static + dynamic) for the first time. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1V processes. Rules of thumb are developed for optimal Vdd and Vth values to be used in future designs. These models show the optimal second Vdd to be approximately half the nominal Vdd while the total power savings are significantly greater than previously anticipated. We describe the impact of level conversion delays and highlight the tradeoff between power savings and critical path count.

Keywords

circuit CAD; circuit optimisation; circuit simulation; delays; integrated circuit design; integrated circuit modelling; low-power electronics; minimisation; power supply circuits; circuit design; critical path count; level conversion delays; models; power reductions; power savings; simultaneous multiple supply and threshold voltage assignment; static-power limited designs; total power minimization; total static/dynamic power; Counting circuits; Degradation; Delay; Energy consumption; Performance loss; Power supplies; Process design; Threshold voltage; Throughput; Thumb;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195048

Filename

1195048