Fast buffer planning and congestion optimization in interconnect-driven floorplanning

In this paper, we study and implement a routability-driven floorplanner with congestion estimation and buffer block planning. We assume that buffers should be inserted at flexible intervals from each other for long enough wires. Under this buffer insertion constraint, our floorplanner estimates congestion by computing the best possible buffer locations for each net and performs probabilistic analysis based on the solution. Dynamic programming is used such that estimations can be done very effectively. Nets are topologically grouped to consider bus-based routing and to facilitate the estimation process. We compare our results with those in paper (C. W. Sham et al, Proc. Int. Symp. on Physical Design, pp. 50-55, 2002) which are the latest results for this problem, and show that our approach can perform better in both quality and runtime.