Title :
Reduction of test inputs for combinational circuits
Author :
Karimi, Bijan ; Johnson, Louis G.
Author_Institution :
Dept. of Electr. Eng., New Haven Univ., West Haven, CT, USA
Abstract :
For a given method of design for testability a mechanism is proposed to reduce the number of test inputs by connecting two or more test inputs together. It is shown that by preprocessing the reconvergent fanouts it is possible to identify and remove some of the redundant reconvergent paths. Reconvergent fanouts with multiple reconvergent gates are investigated, and their application in design for testability is discussed
Keywords :
combinatorial circuits; design for testability; logic gates; logic testing; combinational circuits; design for testability; multiple reconvergent gates; reconvergent fanouts; redundant reconvergent paths; test inputs; Circuit faults; Circuit testing; Combinational circuits; Design for testability; Design methodology; Electrical fault detection; Joining processes; Logic circuits; Logic testing; Programmable logic arrays;
Conference_Titel :
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-0620-1
DOI :
10.1109/MWSCAS.1991.252073
