Comparison between three structures of high speed low-voltage and low-dropout linear regulators

Biasing digital CMOS circuits with rapidly changing supply current requires fast load regulation. Integrating the regulator with no external components on the same chip with the load circuit is attractive for applications with stringent volume and weight requirements. The purpose of this paper is the analysis, design and comparison of three structures of high-speed linear regulators implemented in MOS technologies: a fast regulator recently presented in the literature, that combines a low-bandwidth control loop with fast open-loop buffers, and two structures proposed by the authors - one derived from the standard linear regulator but with improved frequency compensation and the other obtained by combining the first two approaches. The discussion is focused on the response time of these regulators to fast and large variations of the load current, specific to the supplying of digital circuits.