Title :
Robust high-performance low-power carry select adder
Author :
Jeong, Woopyo ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
This paper proposes Dual Transition Skewed Logic (DTSL) based Carry Select Adder (CSA) suitable for processing units requiring low power and high performance with high noise immunity. We implemented 31-bit Carry Select Adders in three different logic styles: Dual Transition Skewed Logic (DTSL), Domino, and conventional static CMOS in TSMC 0.25um technology and compared them in terms of performance, power consumption and layout area. CSA using DTSL shows 36.7% and 17.7% improvements in power dissipation and performance, respectively, over domino, and 40.4% improvement in performance compared to a static CMOS CSA.
Keywords :
CMOS logic circuits; adders; low-power electronics; 0.25 micron; 31 bit; carry select adder; domino circuit; dual transition skewed logic; layout area; low-power design; noise immunity; power dissipation; static CMOS circuit; Adders; CMOS logic circuits; CMOS technology; Circuit noise; Clocks; Digital signal processing chips; Energy consumption; MOSFETs; Robustness; Signal processing algorithms;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195068
