DocumentCode :
3399945
Title :
An algorithm to deal with incremental layout alteration
Author :
Choy, Chiu-Sing ; Cheung, Tsz-Shing
Author_Institution :
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
fYear :
1991
fDate :
14-17 May 1991
Firstpage :
850
Abstract :
Incremental design alteration usually requires complete rework on the IC layout. An algorithm is proposed which tackles the problem in minimum time and creates the least perturbation to the original layout, preserving performance. The algorithm aims at automatic adjustment of layout due to minor change on logic design. As a result, the designer need not re-execute the whole placement process or manually correct the placement. Using dynamic variables to form the database, it is more efficient to implement the algorithm. Results and computation time of the algorithm are also found advantageous
Keywords :
circuit layout CAD; logic CAD; monolithic integrated circuits; IC layout; automatic adjustment; computation time; dynamic variables; incremental layout alteration; logic design; perturbation; placement process; Algorithm design and analysis; Cities and towns; Integrated circuit interconnections; Integrated circuit layout; Logic circuits; Logic design; Partitioning algorithms; Phased arrays; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-0620-1
Type :
conf
DOI :
10.1109/MWSCAS.1991.252079
Filename :
252079
Link To Document :
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