Title : 
Branch predictor design and performance estimation for a high performance embedded microprocessor
         
        
            Author : 
Lee, Sang-Hyuk ; Kim, Il-Kwan ; Choi, Lynn
         
        
            Author_Institution : 
Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea
         
        
        
        
        
        
            Abstract : 
The AE64000 is a 64 bit embedded processor targeting high-end embedded applications such as HDTV, DVD, and 3D graphics. To achieve a higher performance for the AE64000, we design a branch predictor for the processor, and find the optimum parameters for the design through cycle-accurate simulations on SpecINT benchmarks and embedded applications (Dhrystone and Whetstone). In the AE64000, branch prediction is complicated by the instruction folding unit (IFU) of the processor front-end. By predicting on a pre-PC in the IFU, rather than using a PC in the pipeline core, we can effectively eliminate the branch misprediction penalty on a correct prediction. We have developed the AE64000 simulator to evaluate the performance of the designed branch predictor, and selected the optimum branch predictor configuration by considering cost-effectiveness as well as by analyzing the results generated from the AE64000 simulator. The selected branch predictor has been implemented in Verilog and is added to AE64000 pipeline.
         
        
            Keywords : 
circuit optimisation; circuit simulation; hardware description languages; integrated circuit design; logic design; logic simulation; microprocessor chips; parallel architectures; performance evaluation; pipeline processing; 64 bit; AE64000 pipeline; IFU pre-PC prediction; Verilog; branch misprediction penalty; branch prediction; correct prediction; embedded microprocessor; instruction folding unit; optimization; pipeline core PC; predictor performance estimation; processor branch predictor; processor front-end IFU; Analytical models; Application software; Clocks; Costs; Degradation; Embedded computing; High performance computing; Microprocessors; Pipelines; Predictive models;
         
        
        
        
            Conference_Titel : 
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
         
        
            Print_ISBN : 
0-7803-7659-5
         
        
        
            DOI : 
10.1109/ASPDAC.2003.1195072