A highly efficient AES cipher chip

Author

Su, Chih-Pin ; Lin, Tsung-Fu ; Huang, Chih-Tsun ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

561

Lastpage

562

Abstract

We present an efficient hardware implementation of the AES (advanced encryption standard) algorithm, with key expansion capability. Instead of the widely used table-lookup implementation of the S-box, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64% and is easily pipelined to achieve high throughput rate. Using a typical 0.25 μm CMOS technology, the throughput rate is 2.977 Gbps for 128 bit keys, 2.510 Gbps for 192 bit keys, and 2.169 Gbps for 256 bit keys, with a 250 MHz clock. Testability of the design is also considered. The area of the core circuit is about 1,279×1,271 μm².

Keywords

CMOS logic circuits; cryptography; design for testability; integrated circuit design; logic design; pipeline processing; 0.25 micron; 1271 micron; 1279 micron; 128 bit; 192 bit; 2.169 Gbit/s; 2.510 Gbit/s; 2.977 Gbit/s; 250 MHz; 256 bit; AES cipher chip; AES hardware implementation; CMOS; DFT; S-box; S-box throughput rate; advanced encryption standard algorithm; basis transformation technique; cipher chip efficiency; design-for-testability; hardware overhead reduction; key bit size; key expansion capability; pipeline architecture; Application specific integrated circuits; CMOS technology; Clocks; Cryptography; Data security; Field programmable gate arrays; Hardware; NIST; Random access memory; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195078

Filename

1195078