DocumentCode
3400111
Title
Implementation of fast CRC calculation
Author
Henriksson, Tomas ; Liu, Dake
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Sweden
fYear
2003
fDate
21-24 Jan. 2003
Firstpage
563
Lastpage
564
Abstract
CRC is important for error detection in communication systems. With transmission speeds of several Gb/s the high-speed implementation is a bottleneck. A circuit with two parallel calculation units has been implemented in a 0.35 μm process. They use 32 bits and 64 bits parallel input respectively. Chip measurements prove throughput higher than 5.76 Gb/s, which indicates that 10 Gb/s throughput is possible in more modern processes.
Keywords
cyclic redundancy check codes; error detection; error detection codes; integrated circuit design; integrated circuit measurement; logic design; parallel architectures; 0.35 micron; 10 Gbit/s; 32 bit; 5.76 Gbit/s; 64 bit; CRC computation bottleneck; CRC hardware implementation; chip throughput; communication systems; cyclic redundancy check; error detection; parallel calculation units; parallel input; transmission speed; Circuits; Clocks; Concurrent computing; Cyclic redundancy check; Ethernet networks; Logic; Polynomials; Semiconductor device measurement; Silicon; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN
0-7803-7659-5
Type
conf
DOI
10.1109/ASPDAC.2003.1195079
Filename
1195079
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