Title :
Design of a CMOS test chip for package models and I/O characteristics verification
Author :
Despande, Chetan ; Chen, Tom
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
The test chip presented in this design is intended to allow: 1) circuit and package designers to evaluate and validate the accuracy of package models under a variety of environment conditions; 2) system designers to evaluate package/system level signal integrity issue before actual chips are available; and 3) system designers to evaluate on-chip temperatures and to study thermal integrity of packages. The test chip includes a variety of features to achieve these goals. The test chip is fabricated at TSMC in a 0.18 μm CMOS process.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit packaging; thermal management (packaging); 0.18 micron; CMOS; CMOS test chip; I/O characteristics verification; on-chip temperatures; package environment conditions; package level signal integrity; package model accuracy; system level signal integrity; thermal integrity; Capacitance; Circuit testing; Decoding; Frequency; Modems; Packaging; Power supplies; Semiconductor device modeling; Signal design; Temperature sensors;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195080
