A Modified Photonic Switch Architecture based on Fiber Loop Memory

In this paper we have proposed design modifications in fiber optic loop buffer switch. This paper discusses an automatic gain controlling (AGC) scheme for the loop buffer. We have shown that by changing the position of EDFA automatic gain controlling scheme will not be required. We have utilized the availability of filter in tunable wavelength converter (TWC) to reduce number of components in the buffer. Finally we replaced the combination of splitter and filter as in existing architecture by array waveguide grating (AWG) demultiplexer, which reduces the loss in the architecture. The performance evaluation of the switch is done in terms of packet loss probability and delay