Output Phase Assignment for Area and Power Optimization in Multi-level Multi-output Combinational Logic Circuits

In binary decision diagram (BDD) based realization of logic circuits, the area and power consumption is determined by the total number of nodes of the BDD and the expected switching activity of the nodes. A proper polarity selection of the subfunctions can not only reduce the number of BDD nodes, but also the switching. For a multi-output function, more the sharing between the subfunctions, more is the reduction in the number of BDD nodes so also the power. A genetic algorithm based output phase selection of the multi-output function (in BDD form) is proposed in this paper. This idea when applied to a number of benchmark circuits, it is found to reduce the number of nodes in the BDD and hence the area and power. A trade-off has also been done for combined area and power minimization, considering the node switching as the major candidate for power consumption. It has been found that the proposed method minimizes the area by about 3% and power by about 14%