Low-power digital CDMA receiver

Author

Liu, Ju-Sheng ; Chen, I-Hsin ; Yi-Chen Tai ; Jou, Shyh-Jye

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

581

Lastpage

582

Abstract

The advanced design tasks for a digital CDMA receiver are presented in this report. A biased number system and architecture are used to reduce the switching activity to reduce power consumption. A carry-save adder tree is used to speed up the summation of 127 data (3 bits) in the synchronization and date extraction process. Verilog HDL is used to describe this system and the design compiler of Synopsys is used to synthesize our design. Design results show that it can work at 155 MHz (chip rate) with 9913 gate counts by using the Compass 0.35 μm CMOS cell library.

Keywords

CMOS logic circuits; adders; carry logic; code division multiple access; digital radio; hardware description languages; integrated circuit design; logic CAD; mobile radio; radio receivers; 0.35 micron; 155 MHz; 3 bit; Compass CMOS cell library; Synopsys design compiler; Verilog HDL; biased number architecture; biased number system; carry-save adder tree; chip rate; date extraction process; gate counts; low-power digital CDMA receiver; power consumption; receiver design; summation; switching activity; synchronization; Adders; Clocks; Data mining; Decoding; Hardware design languages; Multiaccess communication; Signal design; Signal generators; Synchronization; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195088

Filename

1195088