An efficient IP-level power model for complex digital circuits

Author

Hsu, Chih-Yang ; Liu, Chien-Nan Jimmy ; Jou, Jing-Yang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

610

Lastpage

613

Abstract

In this paper, we propose an efficient IP-level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power, to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS´85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.

Keywords

CMOS logic circuits; Monte Carlo methods; capacitance; circuit simulation; industrial property; integrated circuit modelling; logic simulation; table lookup; IP-level power model; Monte Carlo approach; average power estimation; complex CMOS circuits; complex digital circuits; discharging capacitance mapping; estimation error; lookup table; model accuracy; pattern pairs power consumption; power model efficiency; table dimension; table size; zero-delay charging capacitance; Circuit simulation; Combinational circuits; Computational modeling; Digital circuits; Energy consumption; Estimation error; Semiconductor device modeling; Statistics; System-on-a-chip; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195097

Filename

1195097