Title :
Design flow and methodology for 50M gate ASIC
Author :
Mehrotra, Alok ; van Ginneken, Lukas ; Trivedi, Yatin
Author_Institution :
Magma Design Autom. Inc., Cupertino, CA, USA
Abstract :
This paper presents a methodology for full chip RTL timing closure for very large ASICs. The methodology is based on the concept of a "silicon virtual prototype". The methodology is based on the scalable technique of clustering and cluster placement and leverages the tight integration between the algorithms by means of a common, unified data model.
Keywords :
application specific integrated circuits; circuit optimisation; data models; integrated circuit design; integrated circuit layout; logic design; timing; ASIC design flow; SVP; cluster placement; design methodology; floor plan optimization; full chip RTL timing closure; scalable clustering technique; silicon virtual prototype; unified data model; very large ASIC; Application specific integrated circuits; Design automation; Design methodology; Floors; Productivity; Prototypes; Silicon; Timing; Virtual prototyping; Wire;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195102
