• DocumentCode
    3400711
  • Title

    Cycle time reduction for semiconductor wafer fabrication facilities

  • Author

    Meyersdorf, Doron ; Yang, Taho

  • Author_Institution
    TEFEN, Foster City, CA, USA
  • fYear
    1997
  • fDate
    10-12 Sep 1997
  • Firstpage
    418
  • Lastpage
    423
  • Abstract
    The issue of cycle time reduction and its impact on a company´s competitive edge has been gaining considerable attention recently. Generally speaking, shorter cycle times result in better customer satisfaction, lower work-in-process (WIP), higher yield, and better capacity given tool inventory and facility constraints. This paper provides a brief review of key concepts related to cycle time and describes a methodology for cycle time reduction projects in semiconductor wafer fabrication facilities, including the critically important implementation road map step. Finally, a case study is presented to illustrate the effectiveness and potential gains of the proposed cycle time reduction methodology
  • Keywords
    integrated circuit yield; management; semiconductor device manufacture; capacity; customer satisfaction; cycle time; road map; semiconductor wafer fabrication facility; tool inventory; work-in-process; yield; Cities and towns; Costs; Customer satisfaction; Electronics industry; Fabrication; Lead; Queueing analysis; Roads; Semiconductor device manufacture; Time measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI
  • Conference_Location
    Cambridge, MA
  • ISSN
    1078-8743
  • Print_ISBN
    0-7803-4050-7
  • Type

    conf

  • DOI
    10.1109/ASMC.1997.630772
  • Filename
    630772