• DocumentCode
    3400797
  • Title

    Cross talk driven placement

  • Author

    Lou, Jinan ; Chen, Wei

  • Author_Institution
    Synopsys Inc., Mountain View, CA, USA
  • fYear
    2003
  • fDate
    21-24 Jan. 2003
  • Firstpage
    735
  • Lastpage
    740
  • Abstract
    Due to the fast shrinking of process geometries, signal integrity issues are becoming increasingly critical to the performance and reliability of electronic systems. Traditional post-layout based fixing methodologies quickly break down when hundreds of thousands of nets need to be tailored for signal integrity concerns. In order to achieve signal integrity closure, cross talk, electro-migration, IR drop and other effects must be addressed earlier in the design cycle. In this paper, a new placement algorithm considering cross talk minimization is presented. First, a probabilistic technique is presented to estimate the coupling capacitance during coarse placement. Based on this technique, an effective placement flow is introduced to remove the highly coupled spots via placement density control. By addressing cross talk at placement level with this algorithm, the value and count of the highest post route peak noise were successfully reduced in a set of industrial benchmarks. Furthermore, due to reduced coupling capacitance, the design speed is 8% faster on average in comparison with traditional timing-driven, congestion-aware placement flow.
  • Keywords
    VLSI; capacitance; circuit optimisation; integrated circuit layout; integrated circuit noise; interference (signal); logic design; minimisation; IR drop; VLSI; coarse placement; congestion-aware placement flow; coupling capacitance optimization; cross talk driven placement; cross talk minimization; electro-migration; highly coupled spots; placement density control; post route peak noise reduction; post-layout based fixing; probabilistic technique; reliability; signal integrity; timing-driven placement flow; Capacitance; Coupling circuits; Geometry; Minimization; Routing; Signal design; Signal processing; Topology; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
  • Print_ISBN
    0-7803-7659-5
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2003.1195117
  • Filename
    1195117