Title :
Don´t cares in logic minimization of extended finite state machines
Author :
Jiang, Yunjian ; Brayton, Robert K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
Extended finite state machines (EFSMs) have been proposed to model control oriented systems. A version of this, with the data portion modeled by Presburger arithmetic, has been used in formal verification and test pattern generation. This paper proposes a general logic minimization scheme using don´t care derived from both control and data path. It consists of methods to transfer don´t cares through the data path and to generate logic don´t cares from the data path using quantifier-free Presburger inequalities. Potential applications are discussed and preliminary results validate the scheme on reasonable examples.
Keywords :
circuit CAD; circuit optimisation; digital arithmetic; finite state machines; logic CAD; minimisation of switching nets; EFSM; Presburger arithmetic; control oriented systems model; control path; data path; don´t cares transfer; extended finite state machines; formal verification; logic don´t cares; logic minimization; quantifier-free Presburger inequalities; test pattern generation; Arithmetic; Automata; Circuits; Context modeling; Control system synthesis; Electronic mail; Formal verification; Logic; Minimization; Reachability analysis;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195129
