Multiple test set generation method for LFSR-based BIST

Author

Shi, Youhua ; Zhang, Zhe

Author_Institution

Ohtsuki & Yanagisawa Lab., Waseda Univ., Tokyo, Japan

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

863

Lastpage

868

Abstract

In this paper we propose a new reseeding method for LFSR-based test pattern generation suitable for circuits with random pattern resistant faults. The character of our method is that the proposed test pattern generator (TPG) can work both in normal LFSR mode, to generate pseudorandom test vectors, and in jumping mode to make the TPG jump from a state to the required state (seed of next group). Experimental results indicate that its superiority against other known reseeding techniques with respect to the length of the test sequence and the required area overhead.

Keywords

automatic test pattern generation; built-in self test; design for testability; integrated circuit testing; shift registers; LFSR mode operation; LFSR-based BIST; TPG; jumping mode operation; multiple test set generation method; pseudorandom test vectors; random pattern resistant faults; reseeding method; test area overhead; test pattern generation; test pattern generator; test sequence length; Automatic testing; Built-in self-test; Character generation; Circuit faults; Circuit testing; Costs; Integrated circuit testing; Pattern analysis; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195138

Filename

1195138