Efficient BIST design for sequential machines using FiF-FoF values in machine states

Author

Roy, S. ; Maulik, U. ; Bandyopadhyay, S. ; Basu, S. ; Sikdar, Biplab K.

Author_Institution

Dept. of Comput. Sci. & Technol., Kalyani Gov. Eng. Coll., India

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

875

Lastpage

878

Abstract

This paper introduces a novel BIST-quality metric termed the FiF-FoF (fan-in-factor and fan-out-factor) defined on PSM-states. Based on the FiF-FoF analysis, an efficient scheme is presented that ensures all state codes appear with uniform likelihood at the present state (PS) lines during the test phase. This results in higher fault efficiency in a BIST structure. Experimental results on MCNC benchmarks show that the scheme improves fault efficiency of sequential circuits significantly, with marginal area overhead.

Keywords

built-in self test; fault location; finite state machines; integrated circuit testing; logic testing; sequential circuits; sequential machines; BIST design; BIST structure; BIST-quality metric; FiF-FoF analysis; FiF-FoF values; MCNC benchmarks; fan-in-factor; fan-out-factor; fault efficiency; machine states; marginal area overhead; present state lines; sequential circuits; sequential machines; state code likelihood; test phase; Benchmark testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Computer science; Machine intelligence; Paper technology; Sequential circuits; Strontium;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195140

Filename

1195140