Title :
A new design-for-test technique for reducing SOC test time
Author :
Guru Rao, C.V. ; Chowdhury, D. Roy
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Abstract :
This paper introduces a new design-for-test (DFT) technique for system-on-chip (SOC) designs. It aims to provide the test designer with details of test scheduling, test access mechanism (TAM) design and an integrated test strategy in order to implement an efficient test solution. Post-synthesis simulations are carried out on the net lists of ISCAS´89 benchmark SOCs to prove the allegiance of the proposed algorithm and to realize the DFT. Experiments resulted in a significant reduction of the test time.
Keywords :
design for testability; integrated circuit design; integrated circuit testing; scheduling; system-on-chip; DFT; ISCAS89 benchmark SOC; SOC test time; design-for-test technique; integrated test strategy; net lists; post-synthesis simulations; system-on-chip; test access mechanism design; test scheduling; Benchmark testing; Computer science; Design for testability; Hardware; Helium; Partitioning algorithms; Processor scheduling; Scheduling algorithm; Switches; System testing;
Conference_Titel :
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific
Print_ISBN :
0-7803-7659-5
DOI :
10.1109/ASPDAC.2003.1195141
